The Server Plumbing — Memory Controllers, Retimers & Interconnect
Inside an AI server, thousands of signals have to travel cleanly between GPUs, CPUs, memory, and switches. A handful of specialty chip companies own that plumbing.
An AI rack like the NVIDIA GB200 NVL72 is not one chip — it is 72 GPUs, 36 CPUs, hundreds of memory modules, and tens of thousands of high-speed connections that must all stay in sync at speeds that approach the laws of physics. Three categories of chips make that possible: (1) retimers — tiny silicon "amplifiers" that clean up high-speed PCIe and CXL signals as they hop between chips (Astera Labs is the leader); (2) registering clock drivers and power management ICs — the brains of every DDR5 memory module (Rambus dominates); and (3) custom HBM base dies — the bottom layer of an HBM stack, increasingly customized per hyperscaler (Marvell is positioning for this).
Every GPU connected via PCIe Gen 6, CXL, or UALink needs Astera silicon. Every DDR5 memory module needs Rambus IP. As servers move from standardized to bespoke designs, the design-in cycles get longer and the moats get deeper.
3 names on the watchlist
The PCIe Gen 6 / CXL / UALink retimer chokepoint. Every modern AI GPU connection passes through Astera silicon.
Designs four product families for AI servers: Aries (PCIe Gen 6 retimers), Leo (CXL memory controllers), Taurus (Ethernet smart cable modules), and Scorpio (fabric switches). Each new AI rack architecture needs Astera silicon for the signals to physically reach where they need to go. Per management, $1,000+ of silicon content per XPU. Q1 2026 revenue $308.4M (+93% YoY); Q2 guide $355-365M (above consensus $310M); PCIe Gen 6 was over 1/3 of revenue.
~45% share of DDR5 RCDs. MRDIMM optionality emerging late 2026. The IP-and-silicon hybrid behind every modern AI server's memory subsystem.
Sells DDR5 registering clock drivers (RCDs), power management ICs (PMICs), and IP licenses . Every DDR5 DIMM in an AI server needs an RCD chip — Rambus exited 2025 with mid-40% share (up from "early 40s" in 2024); long-term target 40-50%. PMIC content growing toward 20% target share. Competes vs Renesas and Montage.
Custom ASIC design — supplies AWS Trainium and Microsoft Maia silicon. Emerging custom HBM base die supplier.
A semiconductor company that designs custom chips for hyperscalers . AWS Trainium and Microsoft Maia silicon are co-designed with Marvell. Increasingly important: Marvell is positioning to be the custom HBM base die supplier — the bottom layer of an HBM stack that connects to the GPU — as hyperscalers move toward bespoke memory configurations. FY27 revenue guide $11B. The next chokepoint within the chokepoint.
- Bernstein, TrendForce, Counterpoint · May 2026