Sector VI · 6 chokepoints · 20 names

Memory

The Memory Wall — HBM, DRAM, NAND & the AI Memory Cartel

Imagine an AI chip as a very fast chef. The chef can chop, fry, and plate dishes faster than any human — but only if the ingredients arrive at the cutting board fast enough. If the pantry is across the kitchen and the runner is slow, the chef stands around doing nothing. The chef is the GPU. The pantry is the memory. The runner is the bandwidth between them.

For the past decade, the chefs (chips) got dramatically faster, but the runners (memory bandwidth) didn't keep up. That gap is called the "memory wall," and it's the single biggest reason modern AI is bottlenecked. The fix: stack a tower of memory chips literally on top of each other right next to the GPU, with thousands of tiny wires running between them. That's High Bandwidth Memory — HBM. Every NVIDIA Blackwell, every AMD MI300, every Google TPU, every Amazon Trainium needs 6–8 of these towers per chip.

Only three companies on Earth make HBM: SK Hynix, Samsung, and Micron . NVIDIA has bought essentially every HBM4 wafer for 2026 and 2027. Micron's CEO told CNBC in March 2026 they can only supply about half to two-thirds of what their biggest customers actually want. That is what a chokepoint looks like in real time. And the equipment that stacks HBM (Hanmi's TC bonders) and tests every finished AI chip (Advantest) are even cleaner monopolies than the memory makers themselves.

Sources

Bernstein, TrendForce, Counterpoint · May 2026

Choke 01

The HBM Oligopoly — Three Companies Make the World's AI Memory

HBM3E · HBM4 · HBM4E · Stacked DRAM

Three firms. ~95% of the world's AI memory. NVIDIA has bought all of 2026 and most of 2027 in advance.

HBM is not made the way regular memory is made. It is built by stacking 8 to 12 DRAM dies on top of each other, drilling thousands of tiny vertical wires through them ("through-silicon vias"), and gluing the whole tower to a GPU package . The yields are brutal, the equipment is exotic, and the design rules change with each generation. Only SK Hynix, Samsung, and Micron have mastered it at scale. Per TrendForce, HBM3E supply prices were raised nearly 20% for 2026 contracts; HBM4 has settled in the mid-$500s per stack — roughly 50% above HBM3E. Bernstein estimates HBM was over 50% of DRAM revenue in Q2 2026 (~$7.5B/quarter at SK Hynix alone).

Why this is a chokepoint

Every AI chip in production today needs HBM. There is no substitute. Building a new HBM line takes 18-24 months from first dollar to first revenue. With NVIDIA shipping millions of accelerators per year — each with 6 to 8 HBM stacks — the math simply does not work for demand to meet supply before 2027 at the earliest.

000660.KS SK Hynix

not US-tradable

Price—

~57% of global HBM revenue, ~70% of NVIDIA Rubin HBM4 allocation — the single most important memory company in the AI buildout.

The Korean DRAM and NAND maker that invented HBM in 2013 and has dominated the category ever since. They won the AI lottery by being first to mass-produce 8-high and 12-high HBM stacks at high yield, using a proprietary packaging process called MR-MUF (Mass-Reflow Molded Underfill) that runs cooler than Samsung's competing approach. Market cap crossed $1 trillion USD in May 2026. NYSE ADR listing confidentially filed with the SEC March 2026, targeting 2H 2026 debut.

snapshotFull detail for 000660.KS →

MU Micron Technology

Price

Only US-based HBM maker. ~21% HBM share Q2 2025 (overtook Samsung). Crossed $1T market cap May 26, 2026.

The only US-headquartered memory maker — DRAM, NAND, and HBM. The "Made in America" HBM hedge for hyperscalers who need a non-Korean second source. Building new fabs in Boise, Idaho (HBM and leading-edge DRAM) and Clay, New York with CHIPS Act funding. HBM3E claimed 30% lower power than competitors per management. Per CEO Sanjay Mehrotra on CNBC's Squawk on the Street (March 19, 2026): "We are only able to supply, for our key customers in the midterm, about 50% to two-thirds of their requirements. The gap between demand and supply for all of DRAM, including HBM, is really the highest that we have ever seen."

snapshotFull detail for MU →

005930.KS Samsung Electronics

not US-tradable

Price—

The comeback story in HBM. Lagged through 2024-25; now caught up. Targeting 50% HBM capacity expansion in 2026.

The Korean conglomerate that does everything — memory, foundry, smartphones, displays, consumer electronics. Memory + foundry is the AI-exposed piece. After being caught flat-footed on HBM3E qualification through 2024 and most of 2025, Samsung's HBM4 reportedly passed NVIDIA's 10-11 Gb/s qualification in early 2026, putting them back in the game. Foundry division vertically integrated with in-house SEMES TC bonders.

snapshotFull detail for 005930.KS →

Choke 02

The HBM Stacking Robots — TC Bonders & Hybrid Bonders

Thermo-Compression Bonders · Hybrid Bonders · Sub-Micron Alignment

Every HBM stack on Earth is built by a single Korean company's bonding machines. The successor technology is owned by a single Dutch company.

An HBM stack is built one DRAM die at a time. The dies must be aligned to each other within fractions of a micron — about 1/200th the width of a human hair — then pressed together under heat to fuse the copper connections. The machine that does this is called a thermo-compression (TC) bonder , and one Korean company, Hanmi Semiconductor , makes 71% of them globally. Each TC bonder costs $3-6M. The next-generation process, used starting in HBM4E and HBM5, is called hybrid bonding — where copper pads are joined directly to copper pads without solder, requiring sub-10-nanometer precision. Two companies in the world make hybrid bonders at scale: BE Semiconductor (Netherlands) and Applied Materials (which has a partnership with BESI). This is the cleanest equipment monopoly in the entire semiconductor industry.

Why this is a chokepoint

You cannot make HBM without TC bonders. You cannot make HBM4E or beyond without hybrid bonders. There is no third option, and the lead-time to deliver these machines is 12-18 months. Every HBM ramp announcement at SK Hynix, Samsung, and Micron is fundamentally an order announcement for these two equipment names.

042700.KS Hanmi Semiconductor

not US-tradable

Price—

71% global share of TC bonders — the machine that physically stacks every HBM die on Earth.

Korean equipment maker that builds the thermo-compression (TC) bonders that stack HBM DRAM dies layer-by-layer with sub-micron alignment . Per TechInsights' 2025 TC Bonder Market Report, Hanmi holds 71.2% global share (cumulative $247.7M). Over 90% share specifically in HBM3E 12-layer TC bonders. Closest competitors: SEMES (Samsung's in-house, 13.1%), ASMPT (5.6%), Yamaha Robotics (5.6%). They are now expanding into hybrid bonding too.

snapshotFull detail for 042700.KS →

BESI.AS BE Semiconductor Industries (BESI)

not US-tradable

Price—

Co-leader in hybrid bonders. The HBM4E / HBM5 generation runs on BESI's machines.

Dutch maker of hybrid bonders that join copper-to-copper at less than 10 nanometers of precision , required for HBM4E 16-high stacks and beyond. Applied Materials bought a 9% stake in April 2025, creating an effective "AMAT CMP + BESI bonder" alliance. Bernstein expects all three HBM makers (SK Hynix, Samsung, Micron) to adopt BESI for HBM4E/HBM5 from 2027 onward. The FT reports hybrid bonding revenue went from €36M (2023) to €476M projected (2026).

snapshotFull detail for BESI.AS →

Choke 03

The AI Chip Test Gatekeepers — Every Accelerator Must Pass Through These Machines

Automated Test Equipment (ATE) · HBM Test · Wafer Inspection · Burn-in

Before a single NVIDIA Blackwell, AMD MI400, or Google TPU is shipped, it has to be tested on equipment made by one of two companies. Advantest owns ~70% of that.

Testing a modern AI chip is its own little engineering miracle. The chip has billions of transistors, six to eight HBM stacks, and runs at 1,000+ watts. Each chip is poked by thousands of tiny pins (a "probe card"), fed power, and run through thousands of test vectors — at full speed — to find any bad transistors before the chip is sold. HBM testing is roughly 10x more compute-intensive than regular DRAM testing because the dies are buried inside a 3D stack and have to be tested through the wires that connect them. Two companies dominate: Advantest (Japan, ~70% share in HBM and high-end AI testers) and Teradyne (US, the other half of the test duopoly). Separately, Camtek and Onto Innovation inspect every HBM stack visually with optical metrology.

Why this is a chokepoint

Every accelerator NVIDIA, AMD, Google, AWS, or Microsoft ships passes through these machines. Each generation of AI chip requires longer test times — Rubin tests take longer than Blackwell, which take longer than Hopper. Advantest is ramping capacity from 3,000 systems in 2024 to 5,000 in 2026 to a target of 10,000 by 2027 just to keep up.

6857.T Advantest

not US-tradable

Price—

~70% of HBM/AI tester market. Every NVIDIA Blackwell, AMD MI400, Google TPU, and AWS Trainium tests on its V93000.

Japanese maker of Automated Test Equipment (ATE) . The flagship V93000 platform tests AI SoCs and HBM stacks at speeds the chip will see in the field. Per Chip Stock Investor and multiple analyst reports, Advantest captures ~50-58% of the total ATE market and ~70% in HBM-specific and high-end AI testers. FY26 guide: ¥1,420B revenue, ¥627B operating income.

snapshotFull detail for 6857.T →

TER Teradyne

Price

The "other half" of the test duopoly with Advantest. Magnum EPIC platform is the industry standard for several HBM and custom-ASIC test applications.

US-based ATE leader, also owns Universal Robots (the cobot business — see Robotics sector). Teradyne's Magnum EPIC platform is the industry standard for many HBM testing applications, and Teradyne has gained significant ground at hyperscaler custom-ASIC customers in 2025-26. Stock hit an all-time high of $344.92 in February 2026, up ~245% in 12 months.

snapshotFull detail for TER →

CAMT Camtek

Price

Reference tool for HBM4 inspection across all three major manufacturers. Optical metrology for advanced packaging.

Israeli company that makes optical inspection and metrology systems for advanced semiconductor packaging — the "eyes" that check every HBM stack and chiplet before they ship. The flagship Hawk and Eagle GS platforms use 9th-generation white-light triangulation, giving better coverage than laser-based competitors. Per multiple analyst sources, Camtek is the "reference tool" for HBM4 inspection across SK Hynix, Samsung, and Micron.

snapshotFull detail for CAMT →

ONTO Onto Innovation

Price

Optical metrology for advanced packaging — Camtek's most direct competitor with more diversified exposure.

Diversified competitor to Camtek in optical metrology and inspection for advanced packaging. Smaller HBM exposure than Camtek but broader product portfolio across lithography metrology and process control. The way to own this chokepoint without single-tool concentration risk. Lower-beta way to play the same secular trend.

snapshotFull detail for ONTO →

AEHR Aehr Test Systems

Price

Burn-in / wafer-level stress test — historically SiC-focused, now pivoting to HBM and gallium nitride.

Small-cap, very volatile, single-customer concentration risks. The pivot from SiC burn-in (which slumped with the EV demand softening) to HBM burn-in is what unlocks the next leg if it works. Size very small.

snapshotFull detail for AEHR →

Choke 04

The Server Plumbing — Memory Controllers, Retimers & Interconnect

PCIe Gen 6 · CXL · UALink · DDR5 RCDs · MRDIMM

Inside an AI server, thousands of signals have to travel cleanly between GPUs, CPUs, memory, and switches. A handful of specialty chip companies own that plumbing.

An AI rack like the NVIDIA GB200 NVL72 is not one chip — it is 72 GPUs, 36 CPUs, hundreds of memory modules, and tens of thousands of high-speed connections that must all stay in sync at speeds that approach the laws of physics. Three categories of chips make that possible: (1) retimers — tiny silicon "amplifiers" that clean up high-speed PCIe and CXL signals as they hop between chips (Astera Labs is the leader); (2) registering clock drivers and power management ICs — the brains of every DDR5 memory module (Rambus dominates); and (3) custom HBM base dies — the bottom layer of an HBM stack, increasingly customized per hyperscaler (Marvell is positioning for this).

Why this is a chokepoint

Every GPU connected via PCIe Gen 6, CXL, or UALink needs Astera silicon. Every DDR5 memory module needs Rambus IP. As servers move from standardized to bespoke designs, the design-in cycles get longer and the moats get deeper.

ALAB Astera Labs

Price

The PCIe Gen 6 / CXL / UALink retimer chokepoint. Every modern AI GPU connection passes through Astera silicon.

Designs four product families for AI servers: Aries (PCIe Gen 6 retimers), Leo (CXL memory controllers), Taurus (Ethernet smart cable modules), and Scorpio (fabric switches). Each new AI rack architecture needs Astera silicon for the signals to physically reach where they need to go. Per management, $1,000+ of silicon content per XPU. Q1 2026 revenue $308.4M (+93% YoY); Q2 guide $355-365M (above consensus $310M); PCIe Gen 6 was over 1/3 of revenue.

snapshotFull detail for ALAB →

RMBS Rambus

Price

~45% share of DDR5 RCDs. MRDIMM optionality emerging late 2026. The IP-and-silicon hybrid behind every modern AI server's memory subsystem.

Sells DDR5 registering clock drivers (RCDs), power management ICs (PMICs), and IP licenses . Every DDR5 DIMM in an AI server needs an RCD chip — Rambus exited 2025 with mid-40% share (up from "early 40s" in 2024); long-term target 40-50%. PMIC content growing toward 20% target share. Competes vs Renesas and Montage.

snapshotFull detail for RMBS →

MRVL Marvell Technology

Price

Custom ASIC design — supplies AWS Trainium and Microsoft Maia silicon. Emerging custom HBM base die supplier.

A semiconductor company that designs custom chips for hyperscalers . AWS Trainium and Microsoft Maia silicon are co-designed with Marvell. Increasingly important: Marvell is positioning to be the custom HBM base die supplier — the bottom layer of an HBM stack that connects to the GPU — as hyperscalers move toward bespoke memory configurations. FY27 revenue guide $11B. The next chokepoint within the chokepoint.

snapshotFull detail for MRVL →

Choke 05

The NAND Cycle — Storage for the AI Data Explosion

QLC NAND · Enterprise SSDs · AI Training Storage · NAND Controllers

AI doesn't just need fast memory next to the GPU. It needs petabytes of fast storage somewhere nearby. NAND prices are up 246% in 12 months and the cycle has just turned.

Every AI training job needs to read terabytes of data and write checkpoints every few hours. Every AI inference cluster needs to keep model weights, embeddings, and KV caches close at hand. That's all NAND flash . The category has historically been brutally cyclical (boom-bust-boom), but the combination of AI inference workloads and hyperscaler design wins for QLC flash arrays has driven a vertical price move. Per Kingston's Datacenter SSD Business Manager to TrendForce (December 17, 2025): "NAND prices — already up 246% since Q1 2025 — are likely to climb further." November 2025 contract prices for 512Gb TLC wafers rose over 65% month-over-month. The cycle is early.

Why this is a chokepoint

NAND has the same supply structure as DRAM — a handful of giants (Samsung, SK Hynix, Kioxia, Micron, Sandisk) with multi-year cycle times to add capacity. When AI inference demand stacks on top of normal datacenter demand, prices move violently.

SNDK Sandisk

Price

Pure-play NAND post-WDC spin. Stock +3,800% in 1 year as the NAND supercycle reasserted itself.

The NAND-only entity spun off from Western Digital in early 2025. Owns the BiCS NAND technology and the Yokkaichi/Kitakami fabs (jointly with Kioxia). Q3 FY26 revenue $5.95B with 78% gross margin (+251% YoY). The single best example in this entire document of what happens when a supply-constrained commodity meets an AI demand surge.

snapshotFull detail for SNDK →

285A.T Kioxia Holdings

not US-tradable

Price—

Japanese NAND maker. IPO'd Dec 2024 at ¥1,440; hit ¥66,090 ATH in May 2026 — roughly 43x in 17 months.

The Japanese NAND maker spun out of Toshiba . Jointly operates Yokkaichi and Kitakami fabs with Sandisk. IPO'd December 18, 2024 at ¥1,440 → hit ¥66,090 ATH on May 14, 2026 — roughly 43x. NAND prices surged 246% from Q1 2025 through December 2025. Supply sold out through 2026. AI inference QLC demand exploding. FY2026 revenue ¥2.34T (+37% YoY); US ADR listing planned.

snapshotFull detail for 285A.T →

WDC Western Digital

Price

Post-Sandisk spin, the pure-play HDD survivor — still relevant for AI cold storage. Up +900% YoY.

Post-spin, WDC is pure-play hard disk drives — the cheap, slow storage AI training and inference clusters use for archival, cold data, and large dataset staging. HDDs are still ~10x cheaper per terabyte than NAND. HDD AI capacity is sold out. HAMR (heat-assisted magnetic recording) ramp adds capacity. The "AI archive" thesis is real and AWS, Microsoft, Google are all bidding for capacity.

snapshotFull detail for WDC →

8299.TW Phison Electronics

Price

Dominant client SSD controller maker. PCIe SSD shipments +280% YoY in October 2025.

Taiwanese maker of SSD controllers (the tiny chip inside every SSD that orchestrates reads and writes). Over 20% global share, over 40% in automotive-grade. PCIe SSD shipments +280% YoY October 2025; sold out through 2026. Stock more than doubled in 6 months. Q4 2025 record EPS NT$21.74.

snapshotFull detail for 8299.TW →

SIMO Silicon Motion

Price

Largest merchant SSD controller — Q1 2026 revenue $342M (+105% YoY). The "Phison of the US-listed world."

Makes NAND controllers for client and enterprise SSDs . The largest merchant SSD controller maker — the way to play the NAND cycle without taking direct memory-maker exposure. Q1 2026 revenue $342M (+105% YoY); Q2 guide $393-411M. Risk: Kioxia and other customers in-housing controllers over time.

snapshotFull detail for SIMO →

Choke 06

The AI Storage Software — Pure Storage and the QLC Inference Wave

All-Flash Arrays · DirectFlash · AI Inference Storage

Hyperscalers are starting to design their AI storage in-house, but they need a software partner who knows how to drive QLC NAND at scale. That's Pure Storage.

For two decades, hyperscalers built their own storage systems on commodity hardware and open-source software. But for AI inference at scale, that approach has bumped into physics: QLC NAND (denser, cheaper) is hard to write to without burning out the flash unless you have very sophisticated software to manage wear. Pure Storage has been refining its DirectFlash software for ten years and now has a confirmed top-4 hyperscaler design win (widely reported as Meta) — using Pure's software on hyperscaler-designed hardware, not Pure's own appliances.

Why this is a chokepoint

If QLC becomes the dominant AI inference storage medium (and it likely will), Pure Storage's software franchise has a multi-billion-dollar option on hyperscaler attach. It is an unusual chokepoint — software, not hardware — but durable.

PSTG Pure Storage

Price

Enterprise all-flash storage. Confirmed top-4 hyperscaler design win (widely reported as Meta) — 10-12 EB deployment late 2026.

Builds all-flash enterprise storage appliances and the software that runs them . QLC-based DirectFlash modules deliver flash density at HDD prices for AI inference. The big news: confirmed top-4 hyperscaler design win Q3 2025 (widely reported as Meta) — 10 to 12 exabytes late 2026. Q2 FY2026 revenue $861M (+13%). 90%+ gross margins on the hyperscaler deal because Meta uses ODM hardware running Pure's software.

snapshotFull detail for PSTG →

NTAP NetApp

Price

Enterprise hybrid storage incumbent — quieter AI tailwind, included for completeness.

The older incumbent in enterprise storage. AI storage tailwinds exist but slower. Included for completeness; not a primary chokepoint in this thesis.

snapshotFull detail for NTAP →